In this video we show the high speed digital design flow from Agilent that helps you cut
through the challenges of today’s multi-gigabit standards.
Agilent EEsof’s tools provide views into the time and frequency domains revealing underlying
issues and allowing you to anticipate and address problems, accelerate your design process,
and achieve your design goals.
This diagram illustrates the design flow. We’ll walk through each section starting
with out a SerDes vendor uses Agilent’s electronic system level tool SystemVue, to
create an IBIS AMI model of a multi-gigabit IO of an IC.
SystemVue allows the SerDes architect to create a system level block diagram of the complex
signal processing functions on the IO of today’s chips, then quickly and easily create the
algorithmic modeling interface, or AMI model, for use in the AMI flow that was added to
the IBIS standard in version 5.0. SystemVue reduces the time it takes to generate AMI
code from months to hours.
Now that we have models of the transmit and receive ICs, let’s look at using the advanced
design system, or ADS, for pre-layout design and analysis.
Here’s an ADS schematic ready for pre-layout simulation. Notice the IBIS AMI models of
the SerDes transmitter and receiver generated using the process in the previous step. The
schematic also includes a model of four coupled traces. The trace models in ADS allow you
to model traces on multiple layers with variable width and spacing. This allows you to optimize
these important parameters in pre-layout scenarios. Schematics can also include many other components,
such as vias, discontinuities, and as we’ll see later, S-parameters and fully integrated
EM models.
This schematic is set up to run the ADS channel simulator for fast linear simulation. We could
also use the transient convolution simulator to verify channel performance with fully non-linear
transistor models. Both simulators make use of patented passivity correction and causality
enforcement to ensure accuracy.
ADS also has built-in design guides to help you quickly and easily set up simulations
for standards including PCI express, USB, DDR and HDMI. Here are the results of the
simulation, including waveforms, eye-diagrams, bit error rate and bathtub curves. ADS’
powerful data display allows you to easily post-process the simulation results.
After constraints have been determined and the layout is complete, critical nets can
easily be brought into ADS through tight integration with enterprise layout tools. First, identify
and export the nets. Then bring the nets, along with all the vias and the imperfect
power and ground planes into ADS for post-layout analysis. Now EM simulations can be performed
on this critical portion of the layout structure using Momentum, the integrated 3D planer EM
solver.
The 3D view of our imported layout showing the current distribution from the Momentum
simulation is useful in identifying problem areas. Momentum also calculates the S parameters
for the structure and creates a model for post-layout simulation. Simulation in both
the time and frequency domain helps you solve problems that would be difficult if not impossible
to do with a time domain only simulator.
In this layout of a power delivery network, or PDN, the current distribution is once again
used to identify problem areas. A model can also be created and used to compute the impedance
of the PDN and help to determine decoupling capacitor values.
For 3D geometries that are not planer, such as this SATA connector, EMPro can be used
to run either finite difference time domain or finite element method to analyze the structure.
EMPro interfaces with ADS to create models for channel simulation. 3D components can
be integrated with an ADS layout to simulate overall channel performance.
Now let’s pull it all together in a post-layout analysis of the channel. This is an ADS schematic
ready for post-layout simulation. Notice that now, in addition to built-in trace models,
the schematic includes S-parameter models that can come from simulation or measurement,
and EM models of the critical nets. The results verify that we still have a reasonable eye
opening even with the imperfections introduced by the actual layout.
Finally, it’s always important to validate simulation results with measured data. Here’s
a comparison of measured and simulated eye diagrams for a 16-inch backplane plus daughter
cards. Notice how closely the measured and simulated curves match in the overlaid plot.
In this video we have shown the high speed digital design flow from Agilent EEsof. Agilent
provides the integrated time and frequency domain simulation tools that help you cut
through the challenges of multi-gigabit digital design. For more information, please visit
us at this website.
